library ieee;
use ieee.std_logic_1164.all;

entity music_read is
	port
	(	
	rom_dat : in integer range 0 to 31;
	clk   : in std_logic;
	start : in std_logic;
	meter   : buffer integer range 0 to 31;
	note_code : buffer integer range 0 to 31
	);

end entity;

architecture mr of music_read is
signal cnt:std_logic:='1';
begin

process(clk)
begin
if(start='1')then
	if (rising_edge(clk)) then
	case cnt is 
		when '0'=> note_code<=rom_dat;
		when '1'=> meter<=rom_dat;
		when others=>NULL ;
	end case;
	cnt<=not cnt;	
	end if;
else
	cnt<='1';
	meter<=0;
	note_code<=0;
end if;
end process;
end mr;